1. Field of the Invention vp 52722055.001
The present invention relates to a structure in which insulating property between a conductive layer and an interconnection contact portion can be improved and a method of manufacture thereof, in a semiconductor device having a conductive layer adjacent to the interconnection contact portion.
2. Description of the Background Art
A configuration of a DRAM (Dynamic Random Access Memory) allowing random input/output of information to be stored will be described as an example of a conventional semiconductor device. FIG. 15 is a block diagram showing a configuration of a general DRAM. Referring to FIG. 15, a DRAM 50 includes a memory cell array 51 for storing a data signal, a row and column address buffer 52 externally receiving address signals (A.sub.0 -A.sub.9) for selecting a memory cell, a row decoder 53 and a column decoder 54 for designating a memory cell by decoding the address signals, a sense refresh amplifier 55 amplifying and reading a signal stored in the designated memory cell, a data in buffer 56 and a data out buffer 57 for data input/output, and a clock generator 58 generating a clock signal. Clock generator 58 is connected to receive a row address strobe signal RAS and a column address strobe signal CAS.
In operation, a data signal stored in a memory cell designated by address signals is read by a sense refresh amplifier 24, and is applied to data out buffer 57 through a preamplifier. Data out buffer 57 outputs the data signal in response to a clock signal from a clock generator 58.
FIG. 16 is an equivalent circuit diagram of one memory cell configuring a memory cell array. A memory cell 3 is constituted by one MOS transistor 5 and one capacitor 6. Either of the source region and the drain region of MOS transistor 5 is connected to a bit line 20, and a gate electrode is connected to a word line 8a.
FIG. 17 is a plan structural view of a memory cell, and FIG. 18 is a sectional structural view taken along a line A--A in FIG. 17. Referring to both views, one MOS transistor 5 and one stacked capacitor 6 are formed on a main surface of a silicon substrate 1.
MOS transistor 5 has a pair of source/drain regions 9, 9 and a gate electrode 8a formed on a surface of silicon substrate 1 with a thin gate insulating film 7 interposed. Gate electrode 8a forms a part of a word line.
Stacked capacitor 6 has a multiple layer structure in which a lower electrode 12, a dielectric layer 13 and an upper electrode 14 are provided. One portion of lower electrode 12 is connected to a surface of source/drain regions 9. One of the end portions of capacitor 6 extends above gate electrode 8a with an insulating layer 10 interposed. An upper electrode (a cell plate) 14 of capacitor 6 is formed to cover a whole surface of a memory cell array region. An opening is formed in the vicinity of a bit line contact portion of bit line 20 and source/drain region 9. Referring to FIG. 18, the end portion of upper electrode 14 located above gate electrode 8a defines an end surface of the opening. A first interlayer insulating layer 16 is formed on a surface of upper electrode 14 of capacitor 6. An end surface of first interlayer insulating layer 16 above gate electrode 8a is formed aligned with the end surface of upper electrode 14. Furthermore, a sidewall insulating layer 15 is formed on the end surface of upper electrode 14 of the capacitor and the end surface of first interlayer insulating layer 16.
A conductive pad layer 18 is formed on a surface of source/drain region 9 contacting the bit line. Pad layer 18 extends from the center of source/drain region 9 to surfaces of insulating layer 10, sidewall insulating layer 15 and first interlayer insulating layer 16. A second interlayer insulating layer 17 is formed thick on surfaces of first interlayer insulating layer 16 and pad layer 18. A contact hole 19 is formed in a region located above pad layer 18 of a second interlayer. Bit line 20 is arranged on a surface of interlayer insulating layer 17, and connected to pad layer 18 and source/drain region 9 through contact hole 19.
Manufacturing steps of the memory cell shown in FIG. 18 will be described. FIGS. 19 through 24 are sectional views of the memory cell in the manufacturing steps.
Referring to FIG. 19, a field oxide film 2 is formed in an isolation region of silicon substrate 1 using a LOCOS method. A gate insulating layer film 7 is formed using a thermal oxidation method, and a polycrystal silicon layer is further formed on a surface thereof. A gate electrode 8a is subsequently formed by patterning the polycrystal silicon layer. The surface of silicon substrate 1 is subjected to ion implantation of impurities of a conductivity type different from that of the substrate, using gate electrode 8a as a mask to form source/drain regions 9, 9. Consequently, the periphery of gate electrode 8a is coated with insulating layer 10.
Referring to FIG. 20, after the whole surface is coated with oxide film 30, a prescribed region is etched away. The oxide film 30 is provided to protect regions other than capacitor in forming a capacitor.
Referring to FIG. 21, after a polycrystal silicon layer is deposited on a whole surface, it is patterned to form a lower electrode 12 of the capacitor. A dielectric layer 13 is formed on a surface of lower electrode 12.
Referring to FIG. 22, an upper electrode layer 14 is deposited to cover a whole surface of dielectric layer 13. A first interlayer insulating layer 16 is deposited on a surface of upper electrode layer 14. First interlayer insulating layer 16 and upper electrode layer 14 are patterned. An opening located above one of source/drain regions 9 is formed in first interlayer insulating layer 16 and upper electrode layer 14 by the patterning. The end surfaces of first interlayer insulating layer 16 and upper electrode layer 14, which are facing the opening, are formed to be aligned with each other.
Referring to FIG. 23, an insulating film is deposited on a whole surface, and the insulating film is selectively etched away using anisotropic etching. A second sidewall insulating layer 15 is formed on the aligned end surfaces of first interlayer insulating layer 16 and upper electrode layer 14 in the etching step. The surface of upper electrode 14 is coated with first interlayer insulating layer 16 and second sidewall insulating layer 15.
Referring to FIG. 24, pad layer 18 is formed connected to source/drain region 9. Pad layer 18 extends from the center of source/drain region 9 to the periphery thereof, for example, above second interlayer insulating layer 15 and first interlayer insulating layer 16.
Second interlayer insulating layer 17 is then formed, and contact hole 19 reaching pad layer 18 is formed therein. A bit line 20 is formed on a surface of second interlayer insulating layer 17 and within contact hole 19. A memory cell shown in FIG. 18 is completed by performing the above described steps.
There is a problem of poor insulating property between upper electrode 14 of capacitor 6 and pad layer 18 connected to bit line 20 in a conventional memory cell configuration shown in FIG. 18. Upper electrode 14 of capacitor 6 and pad layer 18 are insulated and isolated mainly by second interlayer insulating layer 15. Referring again to FIG. 23, the second sidewall insulating layer 15 is formed only on sidewalls of upper electrode 14 and first interlayer insulating layer 16 by subjecting the insulating layer deposited on the whole surface of the substrate to anisotropic etching. In the anisotropic etching step, etching is performed more excessively than necessary to etch away the deposited insulating layer in order to expose the surface of source/drain region 9 completely. Because of this overetching, the second sidewall insulating film is liable to be thinner than it was at (the time of) deposition. Thus, the distance between upper electrode 14 and pad layer 18 is reduced and therefore a problem arises that a dielectric breakdown voltage therebetween is decreased.